Scan Based Circuits with Low Power Consumption

In this paper we present a low power scan design method. Nowadays the Boundary Scan (BS) diagnostic access to the circuit input and output cells combined with a scan chain of concatenated internal flip-flops (FF) has become to be a standard. An alternative parallel diagnostic access method called Random Access Scan (RAS) is not used in nowadays ICs because of more difficult routability. In spite of this fact the diagnostic methods with a random access to IC FFs are much less energy consuming than any of the serial diagnostic approaches. They have a disadvantage of higher hardware overhead. In order to maximize power savings and minimize the hardware overhead we have proposed a modified RAS diagnostic access method, which can be used together with the BS. The RAS cells, controlled by the BS TAP controller, replace internal scan chain FFs, which are known as sources of unwanted circuit activity during shifting test patterns. We have calculated the hardware overhead of the RAS circuits and the power dissipated during loading test patterns. We have found that the proposed BS and RAS combination could be very useful for low power design and it does not introduce any additional delay in the functional path.